1. Field of the Invention
The present invention relates to the field of vector processing computer systems; more specifically, the present invention relates to apparatus for and methods of performing arithmetic operations on vectors in a vector processing computer.
2. Prior Art
A number of vector processing systems are known in the applicable art. In general, these systems provide an arithmetic unit which is capable of receiving at least a first vector as a first operand and a second vector as a second operand. The arithmetic unit provides as an output a third vector.
In at least one prior art system, capability is provided for allowing input of a first vector as a first operand, a second vector as a second operand, and a constant as a third operand. For example, the following equation is of this type of format: EQU X=Yop.sub.1 Zop.sub.2 C
Where, C is a constant, op.sub.1 and op.sub.2, are operations (such as multiply, add, etc.) and X, Y and Z are vectors. Such a system is commercially available as the STARDENT 1500 computer system from Stardent Computer, Inc. of Newton, Mass. (formerly known as the TITAN Computer available from Ardent Computer of Sunnyvale, Calif.
A block diagram of a circuit embodied in the STARDENT 1500 computer is shown as FIG. 2--this circuit will be discussed in more detail below in the Detailed Description of the present invention. However, it is worthwhile noting here that, as one aspect of the present invention, it is desired to develop a computer system having an arithmetic unit capable of accepting and executing an instruction which operates on as many as three vector operands. Further, it is an objective of the present invention to develop such a computer while providing compatibility with the prior art STARDENT 1500 computer.
Further, computers such as the STARDENT 1500 computer are capable of processing two vectors, such as vector V1 and V2 and comparing, on an element-by-element basis, the element of these vectors V1 and V2. An output "mask" vector is provided which may indicate, for each vector element in V1 and V2, whether the element in V1 is greater than the element in V2, whether the element in V1 is equal to the element in V2, etc. This type of operation is useful, for example, where it is desired to add elements of vector V1 to elements of vector V2 only where the element of vector V1 is greater than the element of vector V2. The result of this addition operation might be stored in vector V3, elements of vector V3 only being affected when the corresponding element of V1 is greater than the corresponding element in V2. Shown algebraically: EQU mask=V1&gt;V2 EQU V3=V1+V2:mask true
In the STARDENT 1500 computer, mask information is stored in a register which is an integral part of a vector control unit. The mask register of the STARDENT 1500 will be discussed in greater detail below with the discussion of FIG. 2.
It is recognized by the present invention that use of a register in the vector control unit for storing masks leads to several disadvantages. It is an objective of the present invention to provide for more advantageous storage of mask information. For example, it has been recognized that the requirement of providing an available register on the vector unit leads to use of valuable real estate (space) on the vector control unit. Further, unless additional real estate is used, only one register is available. Therefore, it is not possible to easily and directly execute an instruction sequence such as: ##EQU1##
It is desired to provide a computer system unit with capability for allowing operations such as shown in the above example and in general to provide a system which allows for operation on and storage of a plurality of masks.
Further, in the prior art STARDENT 1500 computer, circuitry is provided to allow comparisons of the absolute value of elements in two vectors. The result of this operation is provided as a third vector. In the prior art STARDENT 1500, the values in the third vector are stored with sign information. In the preferred embodiment of the present invention, there exists circuitry to carry out compare operations on the absolute values of elements in vectors in which sign information is not preserved. To allow for compatibility with the prior art STARDENT 1500 computer and to provide similar functionality, it is desired to develop circuitry for saving sign information in the result vector when carrying out such compare operations on the absolute values of vector elements.
As yet another objective of the present invention it is desired to provide an arithmetic unit having relatively low latency, e.g., period of time from supplying operands to the arithmetic unit to receiving a result from the arithmetic unit.
These and other objectives of the present invention will be understood in more detail with reference to the Detailed Description of the Present Invention and the accompanying figures.